This application relates generally to power saving in electronic circuitry, and more particularly to save-restore functionality in integrated circuits.
Integrated circuits (ICs) can comprise various functional blocks, such as input/output, control, encode, and decode. Systems direct power to ICs, and ICs direct power to component functional blocks, to keep ICs and functional blocks (respectively) active and enable them to perform their respective functions promptly on demand. (“Design block” is used herein to refer to either an IC or functional block, when context is applicable to both.) When the functions performed by the design block are not used, the design block can be left idle. However, even while idle, an active design block will continue to consume power to maintain a current state (also called a context or configuration of the design block) comprising the contents of memory elements of the design block, such as flip-flops and registers. If an active design block is powered down to reduce power consumption, its current state can be lost, which can result in an error or require re-initializing the design block, either of which will generally cost power and time to address.
Save-Restore (SR) is a way to enable a design block in a particular operational state to be powered down, and to later be powered back up and returned to the same operational state with reduced power and time cost. To perform SR, the operational state of a design block is stored in on-die memory prior to the design block powering down. When the design block is powered up again, the operational state information is retrieved from the on-die memory and used to recreate the operational state in the design block.
Scan chains are typically used in design-for-testing. Scan chains generally comprise clocked, serially connected flip-flops which are connected to be loaded with data stored by memory elements in a design block when a scan enable signal is asserted. Scan chain lengths (the numbers of cells (e.g., flip-flops) in different scan chains) can vary because of, for example, clock domain mixing restrictions, memory chains, physical design and floor plan requirements, and power domain merging. Scan elements (such as cells and control elements) are generally required to be within the same clock domain (clocked synchronously). Also, separate power domains generally have separate, dedicated scan chains which are active in the power modes provided by respective power domains when the respective power domain is “on” (active).
FIG. 1A shows an example block diagram 100 of a prior art circuit for using scan chains 102 to save a state of a design block. (For convenience, scan chains 102 are referred to as being numbered from the top scan chain 102, CHAIN 1, to the bottom scan chain 102, CHAIN 4.) Bits 104 representing the state of a design block are first loaded from design block memory elements into cells 106 of multiple scan chains 102. (Design blocks, and structure to load state information from design blocks into scan chains 102, are not shown.) Individual bits 104 correspond to states of respective memory elements in the design block. The scan chains 102 are connected to output to an SR control block 108. The SR control block 108 is connected to output control signals, including a clock 130, to the scan chains 102. The SR control block 108 is also connected to store bits 104 outputted from end cells 110 of respective scan chains 102 to a memory 112, where in FIG. 1A (and later Figures), an end cell 110 is intended to identify the cell farthest to the right in each respective chain. For example, CHAIN 1 includes five cells 106, where the fifth cell from left-to-right is also an end cell 110, in that it is connected to output its stored bit to the SR control block 108. As another example, CHAIN 3 (which includes fewer cells 106 as compared to CHAIN 1) includes three cells, where the third cell from left-to-right is also an end cell 110, again connected to output its stored bit 104 to the SR control block 108. The memory 112 has multiple rows 114 and columns 116 of memory cells 118. The SR control block 108 stores bits 104 to a row 114 of memory cells 118 at a time, by generally copying one bit 104 per scan chain 102 end cell 110 to a respective row 114 then being written. Thus, individual columns 116 of memory cells 118 correspond to individual respective scan chains 102; bits 104 read out from a scan chain 102 are stored into memory cells 118 in a corresponding column 116. Rows 114 are numbered one (1) to five (5) (five being the length of the longest of the scan chains 102), and columns 116 are numbered one (1) to four (4) (four being the number of scan chains 102). In FIG. 1B through 1F, the arrow from the SR control block 108 to the memory 112 indicates the row 114 of memory 112 that has just been loaded with data from the scan chains 102.
FIG. 1B shows an example block diagram 120 of the prior art circuit for using scan chains 102 to save a state of a design block, after one clock 130 cycle has passed after FIG. 1A. The scan chains 102 are clocked by the clock signal 130 received from the SR control block 108. The clock 130 causes the scan chains 102 to serially progress bits 104 stored by the cells 106 of the scan chains 102 to adjacent subsequent cells 106, and in the direction of end cells 110, of respective scan chains 102. End cells 110 of scan chains 102 output their stored bits 104 to the SR control block 108, which stores the bits 104, in order, in a row of memory cells 118. Accordingly, in FIG. 1B, the end cell 110 bits 104 (i.e., 1100) from the previous FIG. 1A have been written into the row 114 number (1) of the memory 100. Further, bits 104 in each scan chain 102 have serially progressed by one cell 106 per scan chain 102. Serial progression of bits 104 (also called iterative progression of bits 104 or progressively moving bits 104 herein) means that if bits 104 are stored in serially-connected cells 106 of a scan chain, which for sake of reference consider in the orientation of FIG. 1C as left to right and for connection referred to as cells A, B, and C, then since cells 106 A, B, C are serially-connected A→B→C so that C is the end cell 110, then a single iterative progression will output the bit 104 stored in cell 106 C, cause the bit 104 stored in cell 106 B to be stored in cell 106 C, and cause the bit 104 stored in cell 106 A to be stored in cell 106 B. (Accordingly, the clock 130 is used as a propagation signal, that is, a signal to cause serial progression of bits 104 through a scan chain 102. In some embodiments, a propagation signal other than a clock 130 can be used.)
FIG. 1C shows an example block diagram 122 of the prior art circuit for using scan chains 102 to save a state of a design block, after two clock 130 cycles have passed after FIG. 1A. As shown in FIG. 1C, clock 130 cycles outputted by the SR control block 108 cause the scan chains 102 to iterate the serial progression of the bits 104 stored by the scan chains 102, and to sequentially output the contents of the scan chains 102 to the SR control block 108. Accordingly, in FIG. 1C, the end cell bits (i.e., 0001) from the previous FIG. 1B have been written into the row number (2) of the memory 112. Because bits 104 outputted from end cells 110 of scan chains 102 are stored in sequential rows of corresponding columns 116 of memory cells, the contents of the scan chains 102 are progressively reconstructed in the memory 112, albeit transposed from a scan chain 102 to a memory column 116.
FIG. 1D shows an example block diagram 124 of the prior art circuit for using scan chains 102 to save a state of a design block, after three clock 130 cycles have passed after FIG. 1A. As shown in FIG. 1E, because CHAIN 3 has only three cells 106, it has now outputted all three of its stored bits 104 and is empty.
FIG. 1E shows an example block diagram 126 of the prior art circuit for using scan chains 102 to save a state of a design block, after four clock 130 cycles have passed after FIG. 1A. As shown in FIG. 1E, because CHAIN 2 has only four cells 106, it has now outputted all four of its stored bits 104. Also, because CHAIN 3 was empty after FIG. 1D, there is no bit 104 for the SR control block 108 to store in the memory cell 118 located at row number (4), column (3) (also referred to in (row, column) convention as (4,3)) of the memory 112.
FIG. 1F shows an example block diagram 128 of the prior art circuit for using scan chains 102 to save a state of a design block, after five clock 130 cycles have passed after FIG. 1A. As shown in FIG. 1F, all of the scan chains 102 have now outputted all of their stored bits 104. Also, because CHAINS 2 and 3 were empty after FIG. 1D, there is no bit 104 for the SR control block 108 to store at memory cells 118 (5,2) and (5,3). This means that memory cells 118 (4,3), (5,2), and (5,3) were not assigned by the SR control block 108.
FIG. 1G shows a prior art example block diagram 132 of a memory 112 used to save a state of a design block. Typically, the memory 112 is treated as first-in-first-out (FIFO); this reflects connections already used for the state saving process. Also, as described with respect to the state saving process, the scan chains 102 are clocked together. Therefore, if the memory 112 state as shown in FIG. 1F is used to reload state data into the scan chains 102 by reading row-by-row from the top of the memory 112, data from shorter scan chains 102 (i.e., in columns (2) and (3)) will be iteratively progressed through and out of respective shorter scan chains 102, and unknown data (in the example as shown in FIG. 1F, the contents of (4,3), (5,2), and (5,3)) will be written into and remain in the shorter scan chains 102, causing an inaccurate reproduction of the data that was stored at the save part of the save-reset event. Therefore, the memory 112 is rearranged to prepare for restoration of the design block state. FIG. 1G shows the memory 112 before being rearranged 134 and after being rearranged 136. The memory cells 118 are rearranged so that the last bits 104 written from the shorter scan chains 102 are aligned with the last row 114 of memory cells 118 written by the SR control block 108 (the fifth row 114, because the longest scan chains 102 in FIGS. 1A through 1F are five cells 106 long). Also, the now-unassigned memory cells 118 at (1,2), (1,3) and (2,3) are filled with zeroes. These filler zeroes are first to be loaded into corresponding scan chains 102 (CHAINS 2 and 3, as the scan chain(s) 102 which are shorter than the longest scan chain(s) 102) during a state restoration process (see FIGS. 2A through 2F), and are discarded by shifting beyond the end cell 110 of the shorter chains 110 during the state restoration process. This will result in proper alignment of the state restoration data within the cells 106 of the scan chains 102 when a restore process completes. The memory 112 rearrangement shown in FIG. 1G typically requires software execution or specialized hardware to perform, and adds considerable time to the SR process.
Alternatively, in some prior art embodiments, additional flip-flops can be used to increase the length(s) of the shorter scan chain(s) 102 so that they are as long as the longest scan chain(s) 102, that is, such that each scan chain 102 has a same number of cells 106. This enables proper alignment of the state restoration data within the cells 106 of the scan chains 102 when a restore process completes without memory 112 rearrangement. However, additional flip flops can add significant additional device area usage, as well as additional leakage current when the design block is in a functional mode.
FIG. 2A shows an example block diagram 200 of a prior art circuit for using scan chains 102 to restore a saved state of a design block. A state restore process typically begins when an inactive design block is powered up from a sleep condition. As shown in FIG. 2A, at the beginning of the state restoration process, the memory 112 contains the same data in the same configuration as at the end of the state saving process as shown in FIG. 1G, after the saved data is rearranged 136. The memory 112 is connected to output data read out from a row 114 to the SR control block 108. The SR control block 108 is configured to output data received from the memory 112 to first cells 202 of respective scan chains 102, and to distribute the clock 130 to the scan chains 102. (In FIGS. 2A through 2F, a first cell 202 is intended to identify the cell farthest to the left in each respective scan chain 102.) The clock 130 causes the data received by each of the scan chains 102 from the SR control block 108 to be stored in corresponding cells 106 for each receiving scan chain 102, and for bits 104 (not shown in FIG. 2A) to be iteratively progressed through the serially connected cells 106 of respective scan chains 102. In FIGS. 2B through 2F, the arrow from the memory 112 to the SR control block 108 indicates the row 114 that has just been unloaded from the memory 112 to reload respective cells 106 in each of the scan chains 102.
FIG. 2B shows an example block diagram 202 of the prior art circuit for using scan chains 102 to restore a saved state of a design block, after one clock 130 cycle has passed since FIG. 2A. The clock 130 cycle causes data stored in a first row 114 (row 1) of the memory 112 to be read out from the memory 112 and stored in cells 106 in corresponding ones of the scan chains 102. Accordingly, columns 116 in the memory 112 correspond to respective scan chains 102, so that data read out from memory cells 118 in column 1 are stored in CHAIN 1, data read out from memory cells 118 in column 2 are stored in CHAIN 2, and so on. This means that data are returned to the scan chain 102 they were previously read out from in the save process described with respect to FIGS. 1A through 1G. Note that the zeroes moved into the second and third scan chains 102 (CHAINS 2 and 3) are filler that was added in during the memory 112 rearrangement shown in and described with respect to FIG. 1G. These zeroes will be discarded (i.e., shifted out of a respective scan chain 102) later in the restore process, as described below.
FIG. 2C shows an example block diagram 204 of the prior art circuit for using scan chains 102 to restore a state of a design block, after two clock 130 cycles have passed since FIG. 2A. The clock 130 cycle causes the bits 104 stored in each of the scan chains 102 to be moved through the serially-connected cells 106 in the scan chains 102, and data stored in each of the columns a second row 114 of memory cells 118 to be read out from the memory 112 and stored in corresponding scan chains 102.
FIG. 2D shows an example block diagram 206 of the prior art circuit for using scan chains 102 to restore a saved state of a design block, after three clock 130 cycles have passed since FIG. 2A. The clock 130 cycle causes the bits 104 stored in the scan chains 102 to be moved through the serially-connected cells 106 in the scan chains 102, and data stored in a third row 114 of memory cells 118 to be read out from the memory 112 and stored in corresponding scan chains 102.
FIG. 2E shows an example block diagram 208 of the prior art circuit for using scan chains 102 to restore a saved state of a design block, after a fourth clock 130 cycle has passed since FIG. 2A. The clock 130 cycle causes the bits 104 stored in the scan chains 102 to be moved through the serially-connected cells 106 in the scan chains 102, and data stored in a fourth row 114 of memory cells 118 to be read out from the memory 112 and stored in corresponding scan chains 102. Because the third scan chain 102 (CHAIN 3) is only three cells 106 long, one of the filler zeroes is clocked out of CHAIN 3 and thereby discarded.
FIG. 2F shows an example block diagram 210 of the prior art circuit for using scan chains 102 to restore a saved state of a design block, after a fifth clock 130 cycle has passed since FIG. 2A. The clock 130 cycle causes the bits 104 stored in the scan chains 102 to be moved through the serially-connected cells 106 in the scan chains 102, and data stored in a fifth row 114 of memory cells 118 to be read out from the memory 112 and stored in corresponding scan chains 102. Because the second and third scan chains 102 (CHAINS 2 and 3) are less than five cells 106 long (the length of the longest scan chains 102, the first and fourth scan chains 102), a filler zero is clocked out of each of CHAINS 2 and 3 and thereby discarded. As shown in FIG. 2F, the scan chains 102 now contain the same bits 104, in the same configuration, as at the start of the save process in FIG. 1A. The data contained in the scan chains 102 can then be used to restore the saved state of the design block, reversing the process used to initially load the state data of the design block into the scan chains 102.